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cpu.c
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1/*
2 * This file is part of FFmpeg.
3 *
4 * FFmpeg is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2.1 of the License, or (at your option) any later version.
8 *
9 * FFmpeg is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with FFmpeg; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19#include "config.h"
20
21#if HAVE_SCHED_GETAFFINITY
22#ifndef _GNU_SOURCE
23# define _GNU_SOURCE
24#endif
25#include <sched.h>
26#endif
27
28#include <stddef.h>
29#include <stdint.h>
30#include <stdatomic.h>
31
32#include "attributes.h"
33#include "cpu.h"
34#include "cpu_internal.h"
35#include "opt.h"
36#include "common.h"
37
38#if HAVE_GETPROCESSAFFINITYMASK || HAVE_WINRT
39#include <windows.h>
40#endif
41#if HAVE_SYSCTL
42#if HAVE_SYS_PARAM_H
43#include <sys/param.h>
44#endif
45#include <sys/types.h>
46#include <sys/sysctl.h>
47#endif
48#if HAVE_UNISTD_H
49#include <unistd.h>
50#endif
51
52#if HAVE_GETAUXVAL || HAVE_ELF_AUX_INFO
53#include <sys/auxv.h>
54#endif
55
58
59static int get_cpu_flags(void)
60{
61#if ARCH_MIPS
62 return ff_get_cpu_flags_mips();
63#elif ARCH_AARCH64
65#elif ARCH_ARM
66 return ff_get_cpu_flags_arm();
67#elif ARCH_PPC
68 return ff_get_cpu_flags_ppc();
69#elif ARCH_RISCV
71#elif ARCH_WASM
72 return ff_get_cpu_flags_wasm();
73#elif ARCH_X86
74 return ff_get_cpu_flags_x86();
75#elif ARCH_LOONGARCH
77#endif
78 return 0;
79}
80
108
118
119int av_parse_cpu_caps(unsigned *flags, const char *s)
120{
121 static const AVOption cpuflags_opts[] = {
122 { "flags" , NULL, 0, AV_OPT_TYPE_FLAGS, { .i64 = 0 }, INT64_MIN, INT64_MAX, .unit = "flags" },
123#if ARCH_PPC
124 { "altivec" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ALTIVEC }, .unit = "flags" },
125 { "vsx" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VSX }, .unit = "flags" },
126 { "power8" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_POWER8 }, .unit = "flags" },
127#elif ARCH_X86
128 { "mmx" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX }, .unit = "flags" },
129 { "mmx2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX2 }, .unit = "flags" },
130 { "mmxext" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX2 }, .unit = "flags" },
131 { "sse" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE }, .unit = "flags" },
132 { "sse2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE2 }, .unit = "flags" },
133 { "sse2slow", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE2SLOW }, .unit = "flags" },
134 { "sse3" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE3 }, .unit = "flags" },
135 { "sse3slow", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE3SLOW }, .unit = "flags" },
136 { "ssse3" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSSE3 }, .unit = "flags" },
137 { "atom" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ATOM }, .unit = "flags" },
138 { "sse4.1" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE4 }, .unit = "flags" },
139 { "sse4.2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SSE42 }, .unit = "flags" },
140 { "avx" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX }, .unit = "flags" },
141 { "avxslow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVXSLOW }, .unit = "flags" },
142 { "xop" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_XOP }, .unit = "flags" },
143 { "fma3" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_FMA3 }, .unit = "flags" },
144 { "fma4" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_FMA4 }, .unit = "flags" },
145 { "avx2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX2 }, .unit = "flags" },
146 { "bmi1" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_BMI1 }, .unit = "flags" },
147 { "bmi2" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_BMI2 }, .unit = "flags" },
148 { "3dnow" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOW }, .unit = "flags" },
149 { "3dnowext", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_3DNOWEXT }, .unit = "flags" },
150 { "cmov", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CMOV }, .unit = "flags" },
151 { "aesni", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AESNI }, .unit = "flags" },
152 { "clmul", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_CLMUL }, .unit = "flags" },
153 { "avx512" , NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX512 }, .unit = "flags" },
154 { "avx512icl", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_AVX512ICL }, .unit = "flags" },
155 { "slowgather", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SLOW_GATHER }, .unit = "flags" },
156
157#define CPU_FLAG_P2 AV_CPU_FLAG_CMOV | AV_CPU_FLAG_MMX
158#define CPU_FLAG_P3 CPU_FLAG_P2 | AV_CPU_FLAG_MMX2 | AV_CPU_FLAG_SSE
159#define CPU_FLAG_P4 CPU_FLAG_P3| AV_CPU_FLAG_SSE2
160 { "pentium2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_P2 }, .unit = "flags" },
161 { "pentium3", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_P3 }, .unit = "flags" },
162 { "pentium4", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_P4 }, .unit = "flags" },
163
164#define CPU_FLAG_K62 AV_CPU_FLAG_MMX | AV_CPU_FLAG_3DNOW
165#define CPU_FLAG_ATHLON CPU_FLAG_K62 | AV_CPU_FLAG_CMOV | AV_CPU_FLAG_3DNOWEXT | AV_CPU_FLAG_MMX2
166#define CPU_FLAG_ATHLONXP CPU_FLAG_ATHLON | AV_CPU_FLAG_SSE
167#define CPU_FLAG_K8 CPU_FLAG_ATHLONXP | AV_CPU_FLAG_SSE2
168 { "k6", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMX }, .unit = "flags" },
169 { "k62", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_K62 }, .unit = "flags" },
170 { "athlon", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_ATHLON }, .unit = "flags" },
171 { "athlonxp", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_ATHLONXP }, .unit = "flags" },
172 { "k8", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = CPU_FLAG_K8 }, .unit = "flags" },
173#elif ARCH_ARM
174 { "armv5te", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV5TE }, .unit = "flags" },
175 { "armv6", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV6 }, .unit = "flags" },
176 { "armv6t2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV6T2 }, .unit = "flags" },
177 { "vfp", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFP }, .unit = "flags" },
178 { "vfp_vm", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFP_VM }, .unit = "flags" },
179 { "vfpv3", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFPV3 }, .unit = "flags" },
180 { "neon", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_NEON }, .unit = "flags" },
181 { "setend", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SETEND }, .unit = "flags" },
182#elif ARCH_AARCH64
183 { "armv8", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARMV8 }, .unit = "flags" },
184 { "neon", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_NEON }, .unit = "flags" },
185 { "vfp", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_VFP }, .unit = "flags" },
186 { "dotprod", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_DOTPROD }, .unit = "flags" },
187 { "i8mm", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_I8MM }, .unit = "flags" },
188 { "sve", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SVE }, .unit = "flags" },
189 { "sve2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SVE2 }, .unit = "flags" },
190 { "sme", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SME }, .unit = "flags" },
191 { "crc", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARM_CRC }, .unit = "flags" },
192 { "sme_i16i64", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SME_I16I64 }, .unit = "flags" },
193 { "sme2", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SME2 }, .unit = "flags" },
194 { "pmull", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_PMULL }, .unit = "flags" },
195 { "eor3", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_EOR3 }, .unit = "flags" },
196 { "aes", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_ARM_AES }, .unit = "flags" },
197#elif ARCH_MIPS
198 { "mmi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MMI }, .unit = "flags" },
199 { "msa", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_MSA }, .unit = "flags" },
200#elif ARCH_LOONGARCH
201 { "lsx", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LSX }, .unit = "flags" },
202 { "lasx", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_LASX }, .unit = "flags" },
203#elif ARCH_RISCV
204 { "rvi", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVI }, .unit = "flags" },
205 { "rvb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB }, .unit = "flags" },
206 { "zve32x", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I32 }, .unit = "flags" },
207 { "zve32f", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F32 }, .unit = "flags" },
208 { "zve64x", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_I64 }, .unit = "flags" },
209 { "zve64d", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVV_F64 }, .unit = "flags" },
210 { "zbb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RVB_BASIC }, .unit = "flags" },
211 { "zvbb", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_ZVBB }, .unit = "flags" },
212 { "misaligned", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_RV_MISALIGNED }, .unit = "flags" },
213#elif ARCH_WASM
214 { "simd128", NULL, 0, AV_OPT_TYPE_CONST, { .i64 = AV_CPU_FLAG_SIMD128 }, .unit = "flags" },
215#endif
216 { NULL },
217 };
218 static const AVClass class = {
219 .class_name = "cpuflags",
220 .item_name = av_default_item_name,
221 .option = cpuflags_opts,
222 .version = LIBAVUTIL_VERSION_INT,
223 };
224 const AVClass *pclass = &class;
225
226 return av_opt_eval_flags(&pclass, &cpuflags_opts[0], s, flags);
227}
228
230{
231 static atomic_int printed = 0;
232
233 int nb_cpus = 1;
234 int count = 0;
235#if HAVE_WINRT
236 SYSTEM_INFO sysinfo;
237#endif
238#if HAVE_SCHED_GETAFFINITY && defined(CPU_COUNT)
239 cpu_set_t cpuset;
240
241 CPU_ZERO(&cpuset);
242
243 if (!sched_getaffinity(0, sizeof(cpuset), &cpuset))
244 nb_cpus = CPU_COUNT(&cpuset);
245#elif HAVE_GETPROCESSAFFINITYMASK
246 DWORD_PTR proc_aff, sys_aff;
247 if (GetProcessAffinityMask(GetCurrentProcess(), &proc_aff, &sys_aff))
248 nb_cpus = av_popcount64(proc_aff);
249#elif HAVE_SYSCTL && defined(HW_NCPUONLINE)
250 int mib[2] = { CTL_HW, HW_NCPUONLINE };
251 size_t len = sizeof(nb_cpus);
252
253 if (sysctl(mib, 2, &nb_cpus, &len, NULL, 0) == -1)
254 nb_cpus = 0;
255#elif HAVE_SYSCTL && defined(HW_NCPU)
256 int mib[2] = { CTL_HW, HW_NCPU };
257 size_t len = sizeof(nb_cpus);
258
259 if (sysctl(mib, 2, &nb_cpus, &len, NULL, 0) == -1)
260 nb_cpus = 0;
261#elif HAVE_SYSCONF && defined(_SC_NPROC_ONLN)
262 nb_cpus = sysconf(_SC_NPROC_ONLN);
263#elif HAVE_SYSCONF && defined(_SC_NPROCESSORS_ONLN)
264 nb_cpus = sysconf(_SC_NPROCESSORS_ONLN);
265#elif HAVE_WINRT
266 GetNativeSystemInfo(&sysinfo);
267 nb_cpus = sysinfo.dwNumberOfProcessors;
268#endif
269
271 av_log(NULL, AV_LOG_DEBUG, "detected %d logical cores\n", nb_cpus);
272
274
275 if (count > 0) {
276 nb_cpus = count;
277 av_log(NULL, AV_LOG_DEBUG, "overriding to %d logical cores\n", nb_cpus);
278 }
279
280 return nb_cpus;
281}
282
287
289{
290#if ARCH_MIPS
292#elif ARCH_AARCH64
294#elif ARCH_ARM
296#elif ARCH_PPC
298#elif ARCH_WASM
300#elif ARCH_X86
302#elif ARCH_LOONGARCH
304#endif
305
306 return 8;
307}
308
309#if !ARCH_X86
310unsigned long ff_getauxval(unsigned long type)
311{
312#if HAVE_GETAUXVAL
313 return getauxval(type);
314#elif HAVE_ELF_AUX_INFO
315 unsigned long aux = 0;
316 int ret = elf_aux_info(type, &aux, sizeof(aux));
317 if (ret != 0) {
318 errno = ret;
319 }
320 return aux;
321#else
322 errno = ENOSYS;
323 return 0;
324#endif
325}
326#endif
#define flags(name, subs,...)
Definition cbs_h264.c:74
#define s(width, name)
Definition cbs_vp9.c:198
common internal and external API header
#define av_popcount64
Definition common.h:157
#define ARCH_X86
Definition config.h:35
#define NULL
Definition coverity.c:32
size_t ff_get_cpu_max_align_mips(void)
Definition cpu.c:119
int ff_get_cpu_flags_loongarch(void)
Definition cpu.c:41
int ff_get_cpu_flags_x86(void)
Definition cpu.c:90
int ff_get_cpu_flags_wasm(void)
Definition cpu.c:25
int ff_get_cpu_flags_mips(void)
Definition cpu.c:106
int ff_get_cpu_flags_riscv(void)
Definition cpu.c:52
size_t ff_get_cpu_max_align_ppc(void)
Definition cpu.c:146
size_t ff_get_cpu_max_align_loongarch(void)
Definition cpu.c:51
size_t ff_get_cpu_max_align_wasm(void)
Definition cpu.c:34
int ff_get_cpu_flags_ppc(void)
This function MAY rely on signal() or fork() in order to make sure AltiVec is present.
Definition cpu.c:64
size_t ff_get_cpu_max_align_x86(void)
Definition cpu.c:260
@ AV_OPT_TYPE_CONST
Special option type for declaring named constants.
Definition opt.h:298
@ AV_OPT_TYPE_FLAGS
Underlying C type is unsigned int.
Definition opt.h:254
#define AV_LOG_DEBUG
Stuff which is only useful for libav* developers.
Definition log.h:231
#define AV_LOG_WARNING
Something somehow does not look correct.
Definition log.h:216
const char * av_default_item_name(void *ptr)
Return the context name.
Definition log.c:241
#define LIBAVUTIL_VERSION_INT
Definition version.h:85
int av_opt_eval_flags(void *obj, const AVOption *o, const char *val, int *flags_out)
cl_device_type type
const char * arg
Definition jacosubdec.c:65
int ff_get_cpu_flags_aarch64(void)
Definition cpu.c:214
size_t ff_get_cpu_max_align_aarch64(void)
Definition cpu.c:256
int ff_get_cpu_flags_arm(void)
Definition cpu.c:185
size_t ff_get_cpu_max_align_arm(void)
Definition cpu.c:198
Macro definitions for various function/variable attributes.
size_t av_cpu_max_align(void)
Get the maximum data alignment that may be required by FFmpeg.
Definition cpu.c:288
static int get_cpu_flags(void)
Definition cpu.c:59
void av_force_cpu_flags(int arg)
Disables cpu detection and forces the specified flags.
Definition cpu.c:81
static atomic_int cpu_flags
Definition cpu.c:56
int av_parse_cpu_caps(unsigned *flags, const char *s)
Parse CPU caps from a string and update the given AV_CPU_* flags based on that.
Definition cpu.c:119
void av_cpu_force_count(int count)
Overrides cpu count detection and forces the specified count.
Definition cpu.c:283
unsigned long ff_getauxval(unsigned long type)
Definition cpu.c:310
static atomic_int cpu_count
Definition cpu.c:57
int av_get_cpu_flags(void)
Return the flags which specify extensions supported by the CPU.
Definition cpu.c:109
int av_cpu_count(void)
Definition cpu.c:229
#define AV_CPU_FLAG_DOTPROD
Definition cpu.h:76
#define AV_CPU_FLAG_RVV_I64
Vectors of 64-bit int's *‍/.
Definition cpu.h:100
#define AV_CPU_FLAG_ARMV5TE
Definition cpu.h:68
#define AV_CPU_FLAG_FMA3
Haswell FMA3 functions.
Definition cpu.h:57
#define AV_CPU_FLAG_SSE2
PIV SSE2 functions.
Definition cpu.h:37
#define AV_CPU_FLAG_BMI1
Bit Manipulation Instruction Set 1.
Definition cpu.h:58
#define AV_CPU_FLAG_SVE
Definition cpu.h:78
#define AV_CPU_FLAG_RVI
I (full GPR bank).
Definition cpu.h:97
#define AV_CPU_FLAG_ARM_AES
Definition cpu.h:87
#define AV_CPU_FLAG_VFPV3
Definition cpu.h:72
#define AV_CPU_FLAG_LASX
Definition cpu.h:94
#define AV_CPU_FLAG_SSE3SLOW
SSE3 supported, but usually not faster than regular MMX/SSE (e.g.
Definition cpu.h:42
#define AV_CPU_FLAG_AVX512
AVX-512 functions: requires OS support even if YMM/ZMM registers aren't used.
Definition cpu.h:60
#define AV_CPU_FLAG_VFP
Definition cpu.h:71
#define AV_CPU_FLAG_SSE42
Nehalem SSE4.2 functions.
Definition cpu.h:48
#define AV_CPU_FLAG_NEON
Definition cpu.h:73
#define AV_CPU_FLAG_I8MM
Definition cpu.h:77
#define AV_CPU_FLAG_CMOV
supports cmov instruction
Definition cpu.h:55
#define AV_CPU_FLAG_SVE2
Definition cpu.h:79
#define AV_CPU_FLAG_SSE
SSE functions.
Definition cpu.h:36
#define AV_CPU_FLAG_RVB
B (bit manipulations).
Definition cpu.h:105
#define AV_CPU_FLAG_MMX2
SSE integer functions or AMD MMX ext.
Definition cpu.h:34
#define AV_CPU_FLAG_RVB_BASIC
Basic bit-manipulations.
Definition cpu.h:102
#define AV_CPU_FLAG_SSE4
Penryn SSE4.1 functions.
Definition cpu.h:47
#define AV_CPU_FLAG_FMA4
Bulldozer FMA4 functions.
Definition cpu.h:54
#define AV_CPU_FLAG_RVV_I32
Vectors of 8/16/32-bit int's *‍/.
Definition cpu.h:98
#define AV_CPU_FLAG_VSX
ISA 2.06.
Definition cpu.h:65
#define AV_CPU_FLAG_POWER8
ISA 2.07.
Definition cpu.h:66
#define AV_CPU_FLAG_SETEND
Definition cpu.h:84
#define AV_CPU_FLAG_BMI2
Bit Manipulation Instruction Set 2.
Definition cpu.h:59
#define AV_CPU_FLAG_SSE2SLOW
SSE2 supported, but usually not faster than regular MMX/SSE (e.g.
Definition cpu.h:38
#define AV_CPU_FLAG_MMXEXT
SSE integer functions or AMD MMX ext.
Definition cpu.h:33
#define AV_CPU_FLAG_SSE3
Prescott SSE3 functions.
Definition cpu.h:41
#define AV_CPU_FLAG_AESNI
Advanced Encryption Standard functions.
Definition cpu.h:49
#define AV_CPU_FLAG_LSX
Definition cpu.h:93
#define AV_CPU_FLAG_SME_I16I64
Definition cpu.h:83
#define AV_CPU_FLAG_ARMV6T2
Definition cpu.h:70
#define AV_CPU_FLAG_3DNOWEXT
AMD 3DNowExt.
Definition cpu.h:40
#define AV_CPU_FLAG_XOP
Bulldozer XOP functions.
Definition cpu.h:53
#define AV_CPU_FLAG_ALTIVEC
standard
Definition cpu.h:64
#define AV_CPU_FLAG_EOR3
Definition cpu.h:86
#define AV_CPU_FLAG_ATOM
Atom processor, some SSSE3 instructions are slower.
Definition cpu.h:46
#define AV_CPU_FLAG_VFP_VM
VFPv2 vector mode, deprecated in ARMv7-A and unavailable in various CPUs implementations.
Definition cpu.h:75
#define AV_CPU_FLAG_AVX2
AVX2 functions: requires OS support even if YMM registers aren't used.
Definition cpu.h:56
#define AV_CPU_FLAG_SME2
Definition cpu.h:82
#define AV_CPU_FLAG_SSSE3
Conroe SSSE3 functions.
Definition cpu.h:44
#define AV_CPU_FLAG_ARM_CRC
Definition cpu.h:81
#define AV_CPU_FLAG_AVX512ICL
F/CD/BW/DQ/VL/VNNI/IFMA/VBMI/VBMI2/VPOPCNTDQ/BITALG/GFNI/VAES/VPCLMULQDQ.
Definition cpu.h:61
#define AV_CPU_FLAG_CLMUL
Carry-less Multiplication instruction.
Definition cpu.h:50
#define AV_CPU_FLAG_ARMV8
Definition cpu.h:74
#define AV_CPU_FLAG_PMULL
Definition cpu.h:85
#define AV_CPU_FLAG_SLOW_GATHER
CPU has slow gathers.
Definition cpu.h:62
#define AV_CPU_FLAG_SIMD128
Definition cpu.h:108
#define AV_CPU_FLAG_MSA
Definition cpu.h:90
#define AV_CPU_FLAG_RV_ZVBB
Vector basic bit-manipulations.
Definition cpu.h:103
#define AV_CPU_FLAG_AVXSLOW
AVX supported, but slow when using YMM registers (e.g. Bulldozer).
Definition cpu.h:52
#define AV_CPU_FLAG_RVV_F32
Vectors of float's *‍/.
Definition cpu.h:99
#define AV_CPU_FLAG_ARMV6
Definition cpu.h:69
#define AV_CPU_FLAG_SME
Definition cpu.h:80
#define AV_CPU_FLAG_MMX
standard MMX
Definition cpu.h:32
#define AV_CPU_FLAG_MMI
Definition cpu.h:89
#define AV_CPU_FLAG_RVV_F64
Vectors of double's.
Definition cpu.h:101
#define AV_CPU_FLAG_3DNOW
AMD 3DNOW.
Definition cpu.h:35
#define AV_CPU_FLAG_AVX
AVX functions: requires OS support even if YMM registers aren't used.
Definition cpu.h:51
#define AV_CPU_FLAG_RV_MISALIGNED
Fast misaligned accesses.
Definition cpu.h:104
AVOptions.
@ memory_order_relaxed
Definition stdatomic.h:29
int atomic_int
Definition stdatomic.h:63
#define atomic_load_explicit(object, order)
Definition stdatomic.h:247
#define atomic_exchange_explicit(object, desired, order)
Definition stdatomic.h:259
#define atomic_store_explicit(object, desired, order)
Definition stdatomic.h:253
Describe the class of an AVClass context structure.
Definition log.h:76
const char * class_name
The name of the class; usually it is the same name as the context structure type to which the AVClass...
Definition log.h:81
AVOption.
Definition opt.h:428
#define av_log(a,...)
int len